EPM7064S解密

EPM7064S features ：
    The PSoC programmable system-on-chip family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages.
　　The PSoC architecture, as illustrated in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allow all the device resources to be combined into a complete custom system.
    The PSoC CPLD29x66 family can have up to six I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks.
　　The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).
　　The M8C CPU core is a powerful processor with speeds up to 12MHz, providing a two MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors,to simplify programming of real time embedded events.
    Program execution is timed and protected using the included Sleep Timer and Watch Dog Timer (WDT).Memory includes 32K of Flash for program storage and 2K of SRAM for data storage. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.
　　The PSoC device incorporates flexible internal clock generators,including a 24 MHz IMO (internal main oscillator) accurate to ±4% over temperature and voltage. A low power 32 kHz ILO(internal low speed oscillator) is provided for the Sleep Timer and WDT. If crystal accuracy is  desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.
　　PSoC GPIOs provide connection to the CPU, digital resources,and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt.
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